1. Field of the Invention
The present invention relates to a semiconductor device structure. More particularly, the present invention relates to a gate structure.
2. Description of the Related Art
Because of the high level of integration of deep sub-micron integrated circuits, many device features including line width, contact area and junction depth have been substantially reduced. To increase the performance of the devices despite of such reduction, lowering the resistance and reducing signal delay due to resistance and capacitance (RC-delay) has become immensely important. Thus, in the fabrication of semiconductor devices, a refractory metal silicide layer is frequently formed on polysilicon gate. The polysilicon layer and the refractory metal silicide layer are commonly referred to as a polycide gate. Among various types of refractory metal silicides, the most commonly used metal silicide is tungsten silicide (WSix). A gate structure comprising a polysilicon layer and a tungsten silicide layer is called a “tungsten polycide gate”.
FIG. 1 is a schematic cross-sectional view of a conventional gate structure. In a conventional tungsten polycide gate structure as shown in FIG. 1, a gate dielectric layer 102, a polysilicon layer 104, a tungsten silicide layer 106 and a cap layer 108 are sequentially deposited over a substrate 100 to form a gate structure 110. Then, a thermal oxidation process is performed to form a silicon oxide liner layer 112 on the sidewalls of the gate structure 110. However, in the high-temperature thermal process, a phase transition of the tungsten silicide layer 106 often leads to the lateral extrusions 114. With the continual reduction in the line width of a device, the extrusions 114 may lead to a partial short-circuit between the gate and the conductive part of a contact in a back end processing stage. Ultimately, the performance of the device will be affected.
To prevent a conventional tungsten polycide gate from any extrusions, another conventional technique for forming the gate structure that includes forming an opening in the polysilicon layer and filling tungsten silicide material into the opening has been developed.
FIGS. 2A through 2C are schematic cross-sectional views showing the steps for fabricating a gate structure according to another conventional method. As shown in FIG. 2A, a sacrificial layer 202 and an insulating layer 204 are sequentially formed over a substrate 200. Then, an opening 206 is formed in the insulating layer 204. Thereafter, a gate dielectric layer 208 is formed over the substrate 200 at the bottom of the opening 206.
As shown in FIG. 2B, a polysilicon layer 210 is formed over the substrate 200 without completely filling the opening 206. Then, a tungsten silicide layer 212 is formed over the substrate 200, at least filling the opening 206. After that, part of the polysilicon 210 and the tungsten silicide layer 212 is removed until the surface of the insulating layer 204 is exposed.
As shown in FIG. 2C, the polysilicon 210 and the tungsten silicide layer 212 in the opening 206 is etched back to a certain depth. Then, a cap layer 214 is deposited to fill the opening 206 again. Thereafter, the insulating layer 204 and the sacrificial layer 202 on the substrate 200 is removed to form a gate structure 216. The gate structure 216 comprises the gate dielectric layer 208, the polysilicon layer 210, the tungsten silicide layer 212 and the cap layer 214. Next, a thermal processing operation is performed to form a silicon oxide liner layer 218 on the sidewalls of the polysilicon layer 210 and produce an oxide layer 220 on the substrate 200 at the same time.
Since the cross-sectional area of a tungsten silicide layer 21 is related to the resistance of the gate, increasing the cross-sectional area of the tungsten silicide layer 212 can decrease the resistance of the gate and enhance the performance of the device.